1072 lines
40 KiB
C
1072 lines
40 KiB
C
/*
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* THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND
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* (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
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* CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
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* CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
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* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* Copyright (C) SEMTECH S.A.
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*/
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/*!
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* \file sx1276-LoRa.h
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* \brief SX1276 RF chip driver mode LoRa
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*
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* \version 2.0.B2
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* \date May 6 2013
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* \author Gregory Cristian
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*
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* Last modified by Miguel Luis on Jun 19 2013
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*/
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#ifndef __SX1276_LORA_H__
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#define __SX1276_LORA_H__
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#include "sx1276-LoRaMisc.h"
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/*!
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* SX1276 LoRa General parameters definition
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*/
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typedef struct sLoRaSettings
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{
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uint32_t RFFrequency;
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int8_t Power;
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uint8_t SignalBw; // LORA [0: 7.8 kHz, 1: 10.4 kHz, 2: 15.6 kHz, 3: 20.8 kHz, 4: 31.2 kHz,
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// 5: 41.6 kHz, 6: 62.5 kHz, 7: 125 kHz, 8: 250 kHz, 9: 500 kHz, other: Reserved]
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uint8_t SpreadingFactor; // LORA [6: 64, 7: 128, 8: 256, 9: 512, 10: 1024, 11: 2048, 12: 4096 chips]
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uint8_t ErrorCoding; // LORA [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
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bool CrcOn; // [0: OFF, 1: ON]
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bool ImplicitHeaderOn; // [0: OFF, 1: ON]
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bool RxSingleOn; // [0: Continuous, 1 Single]
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bool FreqHopOn; // [0: OFF, 1: ON]
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uint8_t HopPeriod; // Hops every frequency hopping period symbols
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uint32_t TxPacketTimeout;
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uint32_t RxPacketTimeout;
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uint8_t PayloadLength;
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bool LowDatarateOptimize;
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uint32_t PreambleLen;
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}tLoRaSettings;
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#define NORMALSYMBOLSLENGTH 16
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#define HALF_SLEEP_PERIOD 1000 //ms
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#define HOP_CHANNELS 50
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/*!
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* RF packet definition
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*/
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#define RF_BUFFER_SIZE_MAX 256
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#define RF_BUFFER_SIZE 256
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/*!
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* RF state machine
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*/
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//LoRa
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typedef enum
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{
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RFLR_STATE_IDLE,
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RFLR_STATE_TIMEOUT,
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RFLR_STATE_RX_INIT,
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RFLR_STATE_RX_RUNNING,
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RFLR_STATE_RX_DONE,
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RFLR_STATE_RX_ERR,
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RFLR_STATE_RX_TIMEOUT,
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RFLR_STATE_TX_INIT,
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RFLR_STATE_TX_RUNNING,
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RFLR_STATE_TX_DONE,
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RFLR_STATE_TX_TIMEOUT,
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RFLR_STATE_CAD_INIT,
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RFLR_STATE_CAD_RUNNING,
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RFLR_STATE_CAD_SUCCESS,
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RFLR_STATE_CAD_FAIALED,
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RFLR_STATE_SLEEP,
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/* BEGIN: Added by Barry, 2014/3/5 */
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RFLR_STATE_RX_RECEIVEING,
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RFLR_STATE_RX_VALIDHEAD_TIMEOUT,
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/* END: Added by Barry, 2014/3/5 */
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RFLR_STATE_CSMA_CA,
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}tRFLRStates;
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typedef struct
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{
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u8 rf_DataBuffer[255];
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bool rf_DataBufferValid;
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tRFLRStates rf_state;
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u8 rf_RxPacketSize;
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u8 rf_TxPacketSize;
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bool rf_HeaderValid;
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}st_RF_LoRa_DypeDef;
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#define MODE_NONE 0xA1
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#define CAD_NO_DETECTED 0xA2
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#define CAD_DETECTED 0xA3
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#define DATA_RECEIVED 0xA4
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#define NEED_SLEEP 0xA5
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#define RF_TX_RUNNING 0xA6
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#define RF_TX_END 0xA7
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#define RF_RX_RUNNING 0xA8
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#define RF_RX_END 0xA9
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/*!
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* SX1276 definitions
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*/
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#define XTAL_FREQ 32000000
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#define FREQ_STEP 61.03515625
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/*!
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* SX1276 Internal registers Address
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*/
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#define REG_LR_FIFO 0x00
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// Common settings
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#define REG_LR_OPMODE 0x01
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#define REG_LR_BANDSETTING 0x04
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#define REG_LR_FRFMSB 0x06
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#define REG_LR_FRFMID 0x07
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#define REG_LR_FRFLSB 0x08
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// Tx settings
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#define REG_LR_PACONFIG 0x09
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#define REG_LR_PARAMP 0x0A
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#define REG_LR_OCP 0x0B
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// Rx settings
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#define REG_LR_LNA 0x0C
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// LoRa registers
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#define REG_LR_FIFOADDRPTR 0x0D
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#define REG_LR_FIFOTXBASEADDR 0x0E
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#define REG_LR_FIFORXBASEADDR 0x0F
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#define REG_LR_FIFORXCURRENTADDR 0x10
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#define REG_LR_IRQFLAGSMASK 0x11
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#define REG_LR_IRQFLAGS 0x12
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#define REG_LR_NBRXBYTES 0x13
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#define REG_LR_RXHEADERCNTVALUEMSB 0x14
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#define REG_LR_RXHEADERCNTVALUELSB 0x15
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#define REG_LR_RXPACKETCNTVALUEMSB 0x16
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#define REG_LR_RXPACKETCNTVALUELSB 0x17
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#define REG_LR_MODEMSTAT 0x18
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#define REG_LR_PKTSNRVALUE 0x19
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#define REG_LR_PKTRSSIVALUE 0x1A
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#define REG_LR_RSSIVALUE 0x1B
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#define REG_LR_HOPCHANNEL 0x1C
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#define REG_LR_MODEMCONFIG1 0x1D
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#define REG_LR_MODEMCONFIG2 0x1E
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#define REG_LR_SYMBTIMEOUTLSB 0x1F
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#define REG_LR_PREAMBLEMSB 0x20
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#define REG_LR_PREAMBLELSB 0x21
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#define REG_LR_PAYLOADLENGTH 0x22
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#define REG_LR_PAYLOADMAXLENGTH 0x23
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#define REG_LR_HOPPERIOD 0x24
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#define REG_LR_FIFORXBYTEADDR 0x25
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#define REG_LR_MODEMCONFIG3 0x26
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// end of documented register in datasheet
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// I/O settings
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#define REG_LR_DIOMAPPING1 0x40
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#define REG_LR_DIOMAPPING2 0x41
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// Version
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#define REG_LR_VERSION 0x42
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// Additional settings
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#define REG_LR_PLLHOP 0x44
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#define REG_LR_TCXO 0x4B
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#define REG_LR_PADAC 0x4D
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#define REG_LR_FORMERTEMP 0x5B
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#define REG_LR_BITRATEFRAC 0x5D
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#define REG_LR_AGCREF 0x61
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#define REG_LR_AGCTHRESH1 0x62
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#define REG_LR_AGCTHRESH2 0x63
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#define REG_LR_AGCTHRESH3 0x64
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/*!
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* SX1276 LoRa bit control definition
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*/
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/*!
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* RegFifo
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*/
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/*!
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* RegOpMode
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*/
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#define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F
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#define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default
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#define RFLR_OPMODE_LONGRANGEMODE_ON 0x80
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#define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF
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#define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40
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#define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default
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#define RFLR_OPMODE_FREQMODE_ACCESS_MASK 0xF7
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#define RFLR_OPMODE_FREQMODE_ACCESS_LF 0x08 // Default
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#define RFLR_OPMODE_FREQMODE_ACCESS_HF 0x00
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#define RFLR_OPMODE_MASK 0xF8
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#define RFLR_OPMODE_SLEEP 0x00
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#define RFLR_OPMODE_STANDBY 0x01 // Default
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#define RFLR_OPMODE_SYNTHESIZER_TX 0x02
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#define RFLR_OPMODE_TRANSMITTER 0x03
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#define RFLR_OPMODE_SYNTHESIZER_RX 0x04
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#define RFLR_OPMODE_RECEIVER 0x05
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// LoRa specific modes
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#define RFLR_OPMODE_RECEIVER_SINGLE 0x06
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#define RFLR_OPMODE_CAD 0x07
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/*!
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* RegBandSetting
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*/
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#define RFLR_BANDSETTING_MASK 0x3F
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#define RFLR_BANDSETTING_AUTO 0x00 // Default
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#define RFLR_BANDSETTING_DIV_BY_1 0x40
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#define RFLR_BANDSETTING_DIV_BY_2 0x80
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#define RFLR_BANDSETTING_DIV_BY_6 0xC0
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/*!
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* RegFrf (MHz)
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*/
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#define RFLR_FRFMSB_434_MHZ 0x6C // Default
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#define RFLR_FRFMID_434_MHZ 0x80 // Default
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#define RFLR_FRFLSB_434_MHZ 0x00 // Default
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#define RFLR_FRFMSB_863_MHZ 0xD7
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#define RFLR_FRFMID_863_MHZ 0xC0
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#define RFLR_FRFLSB_863_MHZ 0x00
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#define RFLR_FRFMSB_864_MHZ 0xD8
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#define RFLR_FRFMID_864_MHZ 0x00
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#define RFLR_FRFLSB_864_MHZ 0x00
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#define RFLR_FRFMSB_865_MHZ 0xD8
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#define RFLR_FRFMID_865_MHZ 0x40
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#define RFLR_FRFLSB_865_MHZ 0x00
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#define RFLR_FRFMSB_866_MHZ 0xD8
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#define RFLR_FRFMID_866_MHZ 0x80
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#define RFLR_FRFLSB_866_MHZ 0x00
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#define RFLR_FRFMSB_867_MHZ 0xD8
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#define RFLR_FRFMID_867_MHZ 0xC0
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#define RFLR_FRFLSB_867_MHZ 0x00
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#define RFLR_FRFMSB_868_MHZ 0xD9
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#define RFLR_FRFMID_868_MHZ 0x00
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#define RFLR_FRFLSB_868_MHZ 0x00
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#define RFLR_FRFMSB_869_MHZ 0xD9
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#define RFLR_FRFMID_869_MHZ 0x40
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#define RFLR_FRFLSB_869_MHZ 0x00
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#define RFLR_FRFMSB_870_MHZ 0xD9
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#define RFLR_FRFMID_870_MHZ 0x80
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#define RFLR_FRFLSB_870_MHZ 0x00
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#define RFLR_FRFMSB_902_MHZ 0xE1
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#define RFLR_FRFMID_902_MHZ 0x80
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#define RFLR_FRFLSB_902_MHZ 0x00
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#define RFLR_FRFMSB_903_MHZ 0xE1
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#define RFLR_FRFMID_903_MHZ 0xC0
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#define RFLR_FRFLSB_903_MHZ 0x00
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#define RFLR_FRFMSB_904_MHZ 0xE2
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#define RFLR_FRFMID_904_MHZ 0x00
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#define RFLR_FRFLSB_904_MHZ 0x00
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#define RFLR_FRFMSB_905_MHZ 0xE2
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#define RFLR_FRFMID_905_MHZ 0x40
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#define RFLR_FRFLSB_905_MHZ 0x00
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#define RFLR_FRFMSB_906_MHZ 0xE2
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#define RFLR_FRFMID_906_MHZ 0x80
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#define RFLR_FRFLSB_906_MHZ 0x00
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#define RFLR_FRFMSB_907_MHZ 0xE2
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#define RFLR_FRFMID_907_MHZ 0xC0
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#define RFLR_FRFLSB_907_MHZ 0x00
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#define RFLR_FRFMSB_908_MHZ 0xE3
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#define RFLR_FRFMID_908_MHZ 0x00
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#define RFLR_FRFLSB_908_MHZ 0x00
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#define RFLR_FRFMSB_909_MHZ 0xE3
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#define RFLR_FRFMID_909_MHZ 0x40
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#define RFLR_FRFLSB_909_MHZ 0x00
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#define RFLR_FRFMSB_910_MHZ 0xE3
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#define RFLR_FRFMID_910_MHZ 0x80
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#define RFLR_FRFLSB_910_MHZ 0x00
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#define RFLR_FRFMSB_911_MHZ 0xE3
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#define RFLR_FRFMID_911_MHZ 0xC0
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#define RFLR_FRFLSB_911_MHZ 0x00
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#define RFLR_FRFMSB_912_MHZ 0xE4
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#define RFLR_FRFMID_912_MHZ 0x00
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#define RFLR_FRFLSB_912_MHZ 0x00
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#define RFLR_FRFMSB_913_MHZ 0xE4
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#define RFLR_FRFMID_913_MHZ 0x40
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#define RFLR_FRFLSB_913_MHZ 0x00
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#define RFLR_FRFMSB_914_MHZ 0xE4
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#define RFLR_FRFMID_914_MHZ 0x80
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#define RFLR_FRFLSB_914_MHZ 0x00
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#define RFLR_FRFMSB_915_MHZ 0xE4 // Default
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#define RFLR_FRFMID_915_MHZ 0xC0 // Default
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#define RFLR_FRFLSB_915_MHZ 0x00 // Default
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#define RFLR_FRFMSB_916_MHZ 0xE5
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#define RFLR_FRFMID_916_MHZ 0x00
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#define RFLR_FRFLSB_916_MHZ 0x00
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#define RFLR_FRFMSB_917_MHZ 0xE5
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#define RFLR_FRFMID_917_MHZ 0x40
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#define RFLR_FRFLSB_917_MHZ 0x00
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#define RFLR_FRFMSB_918_MHZ 0xE5
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#define RFLR_FRFMID_918_MHZ 0x80
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#define RFLR_FRFLSB_918_MHZ 0x00
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#define RFLR_FRFMSB_919_MHZ 0xE5
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#define RFLR_FRFMID_919_MHZ 0xC0
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#define RFLR_FRFLSB_919_MHZ 0x00
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#define RFLR_FRFMSB_920_MHZ 0xE6
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#define RFLR_FRFMID_920_MHZ 0x00
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#define RFLR_FRFLSB_920_MHZ 0x00
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#define RFLR_FRFMSB_921_MHZ 0xE6
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#define RFLR_FRFMID_921_MHZ 0x40
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#define RFLR_FRFLSB_921_MHZ 0x00
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#define RFLR_FRFMSB_922_MHZ 0xE6
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#define RFLR_FRFMID_922_MHZ 0x80
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#define RFLR_FRFLSB_922_MHZ 0x00
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#define RFLR_FRFMSB_923_MHZ 0xE6
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#define RFLR_FRFMID_923_MHZ 0xC0
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#define RFLR_FRFLSB_923_MHZ 0x00
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#define RFLR_FRFMSB_924_MHZ 0xE7
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#define RFLR_FRFMID_924_MHZ 0x00
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#define RFLR_FRFLSB_924_MHZ 0x00
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#define RFLR_FRFMSB_925_MHZ 0xE7
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#define RFLR_FRFMID_925_MHZ 0x40
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#define RFLR_FRFLSB_925_MHZ 0x00
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#define RFLR_FRFMSB_926_MHZ 0xE7
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#define RFLR_FRFMID_926_MHZ 0x80
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#define RFLR_FRFLSB_926_MHZ 0x00
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#define RFLR_FRFMSB_927_MHZ 0xE7
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#define RFLR_FRFMID_927_MHZ 0xC0
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#define RFLR_FRFLSB_927_MHZ 0x00
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#define RFLR_FRFMSB_928_MHZ 0xE8
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#define RFLR_FRFMID_928_MHZ 0x00
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#define RFLR_FRFLSB_928_MHZ 0x00
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/*!
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* RegPaConfig
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*/
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#define RFLR_PACONFIG_PASELECT_MASK 0x7F
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#define RFLR_PACONFIG_PASELECT_PABOOST 0x80
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#define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default
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#define RFLR_PACONFIG_MAX_POWER_MASK 0x8F
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#define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0
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/*!
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* RegPaRamp
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*/
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#define RFLR_PARAMP_TXBANDFORCE_MASK 0xEF
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#define RFLR_PARAMP_TXBANDFORCE_BAND_SEL 0x10
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#define RFLR_PARAMP_TXBANDFORCE_AUTO 0x00 // Default
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#define RFLR_PARAMP_MASK 0xF0
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#define RFLR_PARAMP_3400_US 0x00
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#define RFLR_PARAMP_2000_US 0x01
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#define RFLR_PARAMP_1000_US 0x02
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#define RFLR_PARAMP_0500_US 0x03
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#define RFLR_PARAMP_0250_US 0x04
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#define RFLR_PARAMP_0125_US 0x05
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#define RFLR_PARAMP_0100_US 0x06
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#define RFLR_PARAMP_0062_US 0x07
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#define RFLR_PARAMP_0050_US 0x08
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#define RFLR_PARAMP_0040_US 0x09 // Default
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#define RFLR_PARAMP_0031_US 0x0A
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#define RFLR_PARAMP_0025_US 0x0B
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#define RFLR_PARAMP_0020_US 0x0C
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#define RFLR_PARAMP_0015_US 0x0D
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#define RFLR_PARAMP_0012_US 0x0E
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#define RFLR_PARAMP_0010_US 0x0F
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/*!
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* RegOcp
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*/
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#define RFLR_OCP_MASK 0xDF
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#define RFLR_OCP_ON 0x20 // Default
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#define RFLR_OCP_OFF 0x00
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#define RFLR_OCP_TRIM_MASK 0xE0
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#define RFLR_OCP_TRIM_045_MA 0x00
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#define RFLR_OCP_TRIM_050_MA 0x01
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#define RFLR_OCP_TRIM_055_MA 0x02
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#define RFLR_OCP_TRIM_060_MA 0x03
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#define RFLR_OCP_TRIM_065_MA 0x04
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#define RFLR_OCP_TRIM_070_MA 0x05
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#define RFLR_OCP_TRIM_075_MA 0x06
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#define RFLR_OCP_TRIM_080_MA 0x07
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#define RFLR_OCP_TRIM_085_MA 0x08
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#define RFLR_OCP_TRIM_090_MA 0x09
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#define RFLR_OCP_TRIM_095_MA 0x0A
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#define RFLR_OCP_TRIM_100_MA 0x0B // Default
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#define RFLR_OCP_TRIM_105_MA 0x0C
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#define RFLR_OCP_TRIM_110_MA 0x0D
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#define RFLR_OCP_TRIM_115_MA 0x0E
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#define RFLR_OCP_TRIM_120_MA 0x0F
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#define RFLR_OCP_TRIM_130_MA 0x10
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#define RFLR_OCP_TRIM_140_MA 0x11
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#define RFLR_OCP_TRIM_150_MA 0x12
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#define RFLR_OCP_TRIM_160_MA 0x13
|
|
#define RFLR_OCP_TRIM_170_MA 0x14
|
|
#define RFLR_OCP_TRIM_180_MA 0x15
|
|
#define RFLR_OCP_TRIM_190_MA 0x16
|
|
#define RFLR_OCP_TRIM_200_MA 0x17
|
|
#define RFLR_OCP_TRIM_210_MA 0x18
|
|
#define RFLR_OCP_TRIM_220_MA 0x19
|
|
#define RFLR_OCP_TRIM_230_MA 0x1A
|
|
#define RFLR_OCP_TRIM_240_MA 0x1B
|
|
|
|
/*!
|
|
* RegLna
|
|
*/
|
|
#define RFLR_LNA_GAIN_MASK 0x1F
|
|
#define RFLR_LNA_GAIN_G1 0x20 // Default
|
|
#define RFLR_LNA_GAIN_G2 0x40
|
|
#define RFLR_LNA_GAIN_G3 0x60
|
|
#define RFLR_LNA_GAIN_G4 0x80
|
|
#define RFLR_LNA_GAIN_G5 0xA0
|
|
#define RFLR_LNA_GAIN_G6 0xC0
|
|
|
|
#define RFLR_LNA_BOOST_LF_MASK 0xE7
|
|
#define RFLR_LNA_BOOST_LF_DEFAULT 0x00 // Default
|
|
#define RFLR_LNA_BOOST_LF_GAIN 0x08
|
|
#define RFLR_LNA_BOOST_LF_IP3 0x10
|
|
#define RFLR_LNA_BOOST_LF_BOOST 0x18
|
|
|
|
#define RFLR_LNA_RXBANDFORCE_MASK 0xFB
|
|
#define RFLR_LNA_RXBANDFORCE_BAND_SEL 0x04
|
|
#define RFLR_LNA_RXBANDFORCE_AUTO 0x00 // Default
|
|
|
|
#define RFLR_LNA_BOOST_HF_MASK 0xFC
|
|
#define RFLR_LNA_BOOST_HF_OFF 0x00 // Default
|
|
#define RFLR_LNA_BOOST_HF_ON 0x03
|
|
|
|
/*!
|
|
* RegFifoAddrPtr
|
|
*/
|
|
#define RFLR_FIFOADDRPTR 0x00 // Default
|
|
|
|
/*!
|
|
* RegFifoTxBaseAddr
|
|
*/
|
|
#define RFLR_FIFOTXBASEADDR 0x80 // Default
|
|
|
|
/*!
|
|
* RegFifoTxBaseAddr
|
|
*/
|
|
#define RFLR_FIFORXBASEADDR 0x00 // Default
|
|
|
|
/*!
|
|
* RegFifoRxCurrentAddr (Read Only)
|
|
*/
|
|
|
|
/*!
|
|
* RegIrqFlagsMask
|
|
*/
|
|
#define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80
|
|
#define RFLR_IRQFLAGS_RXDONE_MASK 0x40
|
|
#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20
|
|
#define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10
|
|
#define RFLR_IRQFLAGS_TXDONE_MASK 0x08
|
|
#define RFLR_IRQFLAGS_CADDONE_MASK 0x04
|
|
#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02
|
|
#define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01
|
|
|
|
/*!
|
|
* RegIrqFlags
|
|
*/
|
|
#define RFLR_IRQFLAGS_RXTIMEOUT 0x80
|
|
#define RFLR_IRQFLAGS_RXDONE 0x40
|
|
#define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20
|
|
#define RFLR_IRQFLAGS_VALIDHEADER 0x10
|
|
#define RFLR_IRQFLAGS_TXDONE 0x08
|
|
#define RFLR_IRQFLAGS_CADDONE 0x04
|
|
#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02
|
|
#define RFLR_IRQFLAGS_CADDETECTED 0x01
|
|
|
|
/* BEGIN: Added by Barry, 2014/3/5 */
|
|
#define RFLR_IRQFLAGS_ALL_MASK 0xFF
|
|
|
|
/* END: Added by Barry, 2014/3/5 */
|
|
|
|
/*!
|
|
* RegFifoRxNbBytes (Read Only) //
|
|
*/
|
|
|
|
|
|
/*!
|
|
* RegRxHeaderCntValueMsb (Read Only) //
|
|
*/
|
|
|
|
|
|
/*!
|
|
* RegRxHeaderCntValueLsb (Read Only) //
|
|
*/
|
|
|
|
|
|
/*!
|
|
* RegRxPacketCntValueMsb (Read Only) //
|
|
*/
|
|
|
|
|
|
/*!
|
|
* RegRxPacketCntValueLsb (Read Only) //
|
|
*/
|
|
|
|
|
|
/*!
|
|
* RegModemStat (Read Only) //
|
|
*/
|
|
#define RFLR_MODEMSTAT_RX_CR_MASK 0x1F
|
|
#define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0
|
|
|
|
/*!
|
|
* RegPktSnrValue (Read Only) //
|
|
*/
|
|
|
|
|
|
/*!
|
|
* RegPktRssiValue (Read Only) //
|
|
*/
|
|
|
|
|
|
/*!
|
|
* RegRssiValue (Read Only) //
|
|
*/
|
|
|
|
|
|
/*!
|
|
* RegModemConfig1
|
|
*/
|
|
#define RFLR_MODEMCONFIG1_BW_MASK 0x0F
|
|
|
|
#define RFLR_MODEMCONFIG1_BW_7_81_KHZ 0x00
|
|
#define RFLR_MODEMCONFIG1_BW_10_41_KHZ 0x10
|
|
#define RFLR_MODEMCONFIG1_BW_15_62_KHZ 0x20
|
|
#define RFLR_MODEMCONFIG1_BW_20_83_KHZ 0x30
|
|
#define RFLR_MODEMCONFIG1_BW_31_25_KHZ 0x40
|
|
#define RFLR_MODEMCONFIG1_BW_41_66_KHZ 0x50
|
|
#define RFLR_MODEMCONFIG1_BW_62_50_KHZ 0x60
|
|
#define RFLR_MODEMCONFIG1_BW_125_KHZ 0x70 // Default
|
|
#define RFLR_MODEMCONFIG1_BW_250_KHZ 0x80
|
|
#define RFLR_MODEMCONFIG1_BW_500_KHZ 0x90
|
|
|
|
#define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xF1
|
|
#define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x02
|
|
#define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x04 // Default
|
|
#define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x06
|
|
#define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x08
|
|
|
|
#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFE
|
|
#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x01
|
|
#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default
|
|
|
|
/*!
|
|
* RegModemConfig2
|
|
*/
|
|
#define RFLR_MODEMCONFIG2_SF_MASK 0x0F
|
|
#define RFLR_MODEMCONFIG2_SF_6 0x60
|
|
#define RFLR_MODEMCONFIG2_SF_7 0x70 // Default
|
|
#define RFLR_MODEMCONFIG2_SF_8 0x80
|
|
#define RFLR_MODEMCONFIG2_SF_9 0x90
|
|
#define RFLR_MODEMCONFIG2_SF_10 0xA0
|
|
#define RFLR_MODEMCONFIG2_SF_11 0xB0
|
|
#define RFLR_MODEMCONFIG2_SF_12 0xC0
|
|
|
|
#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7
|
|
#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08
|
|
#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00
|
|
|
|
#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 0xFB
|
|
#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON 0x04
|
|
#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF 0x00 // Default
|
|
|
|
#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC
|
|
#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default
|
|
|
|
|
|
/*!
|
|
* RegHopChannel (Read Only)
|
|
*/
|
|
#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F
|
|
#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80
|
|
#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default
|
|
|
|
#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_MASK 0xBF
|
|
#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_ON 0x40
|
|
#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_OFF 0x00 // Default
|
|
|
|
#define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F
|
|
|
|
|
|
/*!
|
|
* RegSymbTimeoutLsb
|
|
*/
|
|
#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default
|
|
|
|
/*!
|
|
* RegPreambleLengthMsb
|
|
*/
|
|
#define RFLR_PREAMBLELENGTHMSB 0x00 // Default
|
|
|
|
/*!
|
|
* RegPreambleLengthLsb
|
|
*/
|
|
#define RFLR_PREAMBLELENGTHLSB 0x08 // Default
|
|
|
|
/*!
|
|
* RegPayloadLength
|
|
*/
|
|
#define RFLR_PAYLOADLENGTH 0x0E // Default
|
|
|
|
/*!
|
|
* RegPayloadMaxLength
|
|
*/
|
|
#define RFLR_PAYLOADMAXLENGTH 0xFF // Default
|
|
|
|
/*!
|
|
* RegHopPeriod
|
|
*/
|
|
#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default
|
|
|
|
|
|
/*!
|
|
* RegDioMapping1
|
|
*/
|
|
#define RFLR_DIOMAPPING1_DIO0_MASK 0x3F
|
|
#define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default
|
|
#define RFLR_DIOMAPPING1_DIO0_01 0x40
|
|
#define RFLR_DIOMAPPING1_DIO0_10 0x80
|
|
#define RFLR_DIOMAPPING1_DIO0_11 0xC0
|
|
|
|
#define RFLR_DIOMAPPING1_DIO1_MASK 0xCF
|
|
#define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default
|
|
#define RFLR_DIOMAPPING1_DIO1_01 0x10
|
|
#define RFLR_DIOMAPPING1_DIO1_10 0x20
|
|
#define RFLR_DIOMAPPING1_DIO1_11 0x30
|
|
|
|
#define RFLR_DIOMAPPING1_DIO2_MASK 0xF3
|
|
#define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default
|
|
#define RFLR_DIOMAPPING1_DIO2_01 0x04
|
|
#define RFLR_DIOMAPPING1_DIO2_10 0x08
|
|
#define RFLR_DIOMAPPING1_DIO2_11 0x0C
|
|
|
|
#define RFLR_DIOMAPPING1_DIO3_MASK 0xFC
|
|
#define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default
|
|
#define RFLR_DIOMAPPING1_DIO3_01 0x01
|
|
#define RFLR_DIOMAPPING1_DIO3_10 0x02
|
|
#define RFLR_DIOMAPPING1_DIO3_11 0x03
|
|
|
|
/*!
|
|
* RegDioMapping2
|
|
*/
|
|
#define RFLR_DIOMAPPING2_DIO4_MASK 0x3F
|
|
#define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default
|
|
#define RFLR_DIOMAPPING2_DIO4_01 0x40
|
|
#define RFLR_DIOMAPPING2_DIO4_10 0x80
|
|
#define RFLR_DIOMAPPING2_DIO4_11 0xC0
|
|
|
|
#define RFLR_DIOMAPPING2_DIO5_MASK 0xCF
|
|
#define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default
|
|
#define RFLR_DIOMAPPING2_DIO5_01 0x10
|
|
#define RFLR_DIOMAPPING2_DIO5_10 0x20
|
|
#define RFLR_DIOMAPPING2_DIO5_11 0x30
|
|
|
|
#define RFLR_DIOMAPPING2_MAP_MASK 0xFE
|
|
#define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01
|
|
#define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default
|
|
|
|
/*!
|
|
* RegVersion (Read Only)
|
|
*/
|
|
|
|
/*!
|
|
* RegAgcRef
|
|
*/
|
|
|
|
/*!
|
|
* RegAgcThresh1
|
|
*/
|
|
|
|
/*!
|
|
* RegAgcThresh2
|
|
*/
|
|
|
|
/*!
|
|
* RegAgcThresh3
|
|
*/
|
|
|
|
/*!
|
|
* RegFifoRxByteAddr (Read Only)
|
|
*/
|
|
|
|
/*!
|
|
* RegPllHop
|
|
*/
|
|
#define RFLR_PLLHOP_FASTHOP_MASK 0x7F
|
|
#define RFLR_PLLHOP_FASTHOP_ON 0x80
|
|
#define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default
|
|
|
|
/*!
|
|
* RegTcxo
|
|
*/
|
|
#define RFLR_TCXO_TCXOINPUT_MASK 0xEF
|
|
#define RFLR_TCXO_TCXOINPUT_ON 0x10
|
|
#define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default
|
|
|
|
/*!
|
|
* RegPaDac
|
|
*/
|
|
#define RFLR_PADAC_20DBM_MASK 0xF8
|
|
#define RFLR_PADAC_20DBM_ON 0x07
|
|
#define RFLR_PADAC_20DBM_OFF 0x04 // Default
|
|
|
|
/*!
|
|
* RegPll
|
|
*/
|
|
#define RFLR_PLL_BANDWIDTH_MASK 0x3F
|
|
#define RFLR_PLL_BANDWIDTH_75 0x00
|
|
#define RFLR_PLL_BANDWIDTH_150 0x40
|
|
#define RFLR_PLL_BANDWIDTH_225 0x80
|
|
#define RFLR_PLL_BANDWIDTH_300 0xC0 // Default
|
|
|
|
/*!
|
|
* RegPllLowPn
|
|
*/
|
|
#define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F
|
|
#define RFLR_PLLLOWPN_BANDWIDTH_75 0x00
|
|
#define RFLR_PLLLOWPN_BANDWIDTH_150 0x40
|
|
#define RFLR_PLLLOWPN_BANDWIDTH_225 0x80
|
|
#define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default
|
|
|
|
/*!
|
|
* RegModemConfig3
|
|
*/
|
|
#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK 0xF7
|
|
#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON 0x08
|
|
#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF 0x00 // Default
|
|
|
|
#define RFLR_MODEMCONFIG3_AGCAUTO_MASK 0xFB
|
|
#define RFLR_MODEMCONFIG3_AGCAUTO_ON 0x04 // Default
|
|
#define RFLR_MODEMCONFIG3_AGCAUTO_OFF 0x00
|
|
|
|
|
|
/* BEGIN: Added by Barry, 2014/3/4 */
|
|
typedef enum
|
|
{
|
|
|
|
DIO0_RxDone = RFLR_DIOMAPPING1_DIO0_00,
|
|
DIO0_TxDone = RFLR_DIOMAPPING1_DIO0_01,
|
|
DIO0_CadDone = RFLR_DIOMAPPING1_DIO0_10,
|
|
DIO0_unused = RFLR_DIOMAPPING1_DIO0_11,
|
|
|
|
|
|
DIO1_RxTimeout = RFLR_DIOMAPPING1_DIO1_00,
|
|
DIO1_FhssCC = RFLR_DIOMAPPING1_DIO1_01,
|
|
DIO1_CadDetected = RFLR_DIOMAPPING1_DIO1_10,
|
|
DIO1_unused = RFLR_DIOMAPPING1_DIO1_11,
|
|
|
|
|
|
DIO2_FhssCC = RFLR_DIOMAPPING1_DIO2_00,
|
|
//DIO2_FhssCC = RFLR_DIOMAPPING1_DIO2_01,
|
|
//DIO2_FhssCC = RFLR_DIOMAPPING1_DIO2_10,
|
|
DIO2_unused = RFLR_DIOMAPPING1_DIO2_11,
|
|
|
|
|
|
DIO3_CadDone = RFLR_DIOMAPPING1_DIO3_00,
|
|
DIO3_ValidHeader = RFLR_DIOMAPPING1_DIO3_01,
|
|
DIO3_PayloadCrcError = RFLR_DIOMAPPING1_DIO3_10,
|
|
DIO3_unused = RFLR_DIOMAPPING1_DIO3_11,
|
|
|
|
|
|
DIO4_CadDetected = RFLR_DIOMAPPING2_DIO4_00,
|
|
DIO4_PllLock = RFLR_DIOMAPPING2_DIO4_01,
|
|
//DIO4_PllLock = RFLR_DIOMAPPING2_DIO4_10,
|
|
DIO4_unused = RFLR_DIOMAPPING2_DIO4_11,
|
|
|
|
|
|
DIO5_ModeReady = RFLR_DIOMAPPING2_DIO5_00,
|
|
DIO5_ClkOut = RFLR_DIOMAPPING2_DIO5_01,
|
|
//DIO5_ClkOut = RFLR_DIOMAPPING2_DIO5_10,
|
|
DIO5_unused = RFLR_DIOMAPPING2_DIO5_11,
|
|
}em_GDOxMap_typeDef;
|
|
|
|
|
|
typedef struct
|
|
{
|
|
em_GDOxMap_typeDef GDO0Config;
|
|
em_GDOxMap_typeDef GDO1Config;
|
|
em_GDOxMap_typeDef GDO2Config;
|
|
em_GDOxMap_typeDef GDO3Config;
|
|
em_GDOxMap_typeDef GDO4Config;
|
|
em_GDOxMap_typeDef GDO5Config;
|
|
}st_GDOx_Config;
|
|
|
|
#define DEFAULT_DIO_config {DIO0_RxDone, DIO1_RxTimeout, DIO2_FhssCC, DIO3_CadDone, DIO4_CadDetected, DIO5_ModeReady}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* END: Added by Barry, 2014/3/4 */
|
|
|
|
/*!
|
|
* RegFormerTemp
|
|
*/
|
|
|
|
typedef struct sSX1276LR
|
|
{
|
|
uint8_t RegFifo; // 0x00
|
|
// Common settings
|
|
uint8_t RegOpMode; // 0x01
|
|
uint8_t RegRes02; // 0x02
|
|
uint8_t RegRes03; // 0x03
|
|
uint8_t RegBandSetting; // 0x04
|
|
uint8_t RegRes05; // 0x05
|
|
uint8_t RegFrfMsb; // 0x06
|
|
uint8_t RegFrfMid; // 0x07
|
|
uint8_t RegFrfLsb; // 0x08
|
|
// Tx settings
|
|
uint8_t RegPaConfig; // 0x09
|
|
uint8_t RegPaRamp; // 0x0A
|
|
uint8_t RegOcp; // 0x0B
|
|
// Rx settings
|
|
uint8_t RegLna; // 0x0C
|
|
// LoRa registers
|
|
uint8_t RegFifoAddrPtr; // 0x0D
|
|
uint8_t RegFifoTxBaseAddr; // 0x0E
|
|
uint8_t RegFifoRxBaseAddr; // 0x0F
|
|
uint8_t RegFifoRxCurrentAddr; // 0x10
|
|
uint8_t RegIrqFlagsMask; // 0x11
|
|
uint8_t RegIrqFlags; // 0x12
|
|
uint8_t RegNbRxBytes; // 0x13
|
|
uint8_t RegRxHeaderCntValueMsb; // 0x14
|
|
uint8_t RegRxHeaderCntValueLsb; // 0x15
|
|
uint8_t RegRxPacketCntValueMsb; // 0x16
|
|
uint8_t RegRxPacketCntValueLsb; // 0x17
|
|
uint8_t RegModemStat; // 0x18
|
|
uint8_t RegPktSnrValue; // 0x19
|
|
uint8_t RegPktRssiValue; // 0x1A
|
|
uint8_t RegRssiValue; // 0x1B
|
|
uint8_t RegHopChannel; // 0x1C
|
|
uint8_t RegModemConfig1; // 0x1D
|
|
uint8_t RegModemConfig2; // 0x1E
|
|
uint8_t RegSymbTimeoutLsb; // 0x1F
|
|
uint8_t RegPreambleMsb; // 0x20
|
|
uint8_t RegPreambleLsb; // 0x21
|
|
uint8_t RegPayloadLength; // 0x22
|
|
uint8_t RegMaxPayloadLength; // 0x23
|
|
uint8_t RegHopPeriod; // 0x24
|
|
uint8_t RegFifoRxByteAddr; // 0x25
|
|
uint8_t RegModemConfig3; // 0x26
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uint8_t RegTestReserved27[0x30 - 0x27]; // 0x27-0x30
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uint8_t RegTestReserved31; // 0x31
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uint8_t RegTestReserved32[0x40 - 0x32]; // 0x32-0x40
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// I/O settings
|
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uint8_t RegDioMapping1; // 0x40
|
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uint8_t RegDioMapping2; // 0x41
|
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// Version
|
|
uint8_t RegVersion; // 0x42
|
|
// Additional settings
|
|
uint8_t RegAgcRef; // 0x43
|
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uint8_t RegAgcThresh1; // 0x44
|
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uint8_t RegAgcThresh2; // 0x45
|
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uint8_t RegAgcThresh3; // 0x46
|
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// Test
|
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uint8_t RegTestReserved47[0x4B - 0x47]; // 0x47-0x4A
|
|
// Additional settings
|
|
uint8_t RegPllHop; // 0x4B
|
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uint8_t RegTestReserved4C; // 0x4C
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uint8_t RegPaDac; // 0x4D
|
|
// Test
|
|
uint8_t RegTestReserved4E[0x58-0x4E]; // 0x4E-0x57
|
|
// Additional settings
|
|
uint8_t RegTcxo; // 0x58
|
|
// Test
|
|
uint8_t RegTestReserved59; // 0x59
|
|
// Test
|
|
uint8_t RegTestReserved5B; // 0x5B
|
|
// Additional settings
|
|
uint8_t RegPll; // 0x5C
|
|
// Test
|
|
uint8_t RegTestReserved5D; // 0x5D
|
|
// Additional settings
|
|
uint8_t RegPllLowPn; // 0x5E
|
|
// Test
|
|
uint8_t RegTestReserved5F[0x6C - 0x5F]; // 0x5F-0x6B
|
|
// Additional settings
|
|
uint8_t RegFormerTemp; // 0x6C
|
|
// Test
|
|
uint8_t RegTestReserved6D[0x71 - 0x6D]; // 0x6D-0x70
|
|
}tSX1276LR;
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extern tSX1276LR* SX1276LR;
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/*!
|
|
* \brief Initializes the SX1276
|
|
*/
|
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void SX1276LoRaInit( void );
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/*!
|
|
* \brief Sets the SX1276 to datasheet default values
|
|
*/
|
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void SX1276LoRaSetDefaults( void );
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/*!
|
|
* \brief Enables/Disables the LoRa modem
|
|
*
|
|
* \param [IN]: enable [true, false]
|
|
*/
|
|
void SX1276LoRaSetLoRaOn( bool enable );
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|
|
/*!
|
|
* \brief Sets the SX1276 operating mode
|
|
*
|
|
* \param [IN] opMode New operating mode
|
|
*/
|
|
void SX1276LoRaSetOpMode( uint8_t opMode );
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/*!
|
|
* \brief Gets the SX1276 operating mode
|
|
*
|
|
* \retval opMode Current operating mode
|
|
*/
|
|
uint8_t SX1276LoRaGetOpMode( void );
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|
|
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/*!
|
|
* \brief Reads the current Rx gain setting
|
|
*
|
|
* \retval rxGain Current gain setting
|
|
*/
|
|
uint8_t SX1276LoRaReadRxGain( void );
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|
|
|
/*!
|
|
* \brief Trigs and reads the current RSSI value
|
|
*
|
|
* \retval rssiValue Current RSSI value in [dBm]
|
|
*/
|
|
double SX1276LoRaReadRssi( void );
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|
|
|
/*!
|
|
* \brief Gets the Rx gain value measured while receiving the packet
|
|
*
|
|
* \retval rxGainValue Current Rx gain value
|
|
*/
|
|
uint8_t SX1276LoRaGetPacketRxGain( void );
|
|
|
|
/*!
|
|
* \brief Gets the SNR value measured while receiving the packet
|
|
*
|
|
* \retval snrValue Current SNR value in [dB]
|
|
*/
|
|
int8_t SX1276LoRaGetPacketSnr( void );
|
|
|
|
/*!
|
|
* \brief Gets the RSSI value measured while receiving the packet
|
|
*
|
|
* \retval rssiValue Current RSSI value in [dBm]
|
|
*/
|
|
double SX1276LoRaGetPacketRssi( void );
|
|
|
|
/*!
|
|
* \brief Sets the radio in Rx mode. Waiting for a packet
|
|
*/
|
|
void SX1276LoRaStartRx( void );
|
|
|
|
/*!
|
|
* \brief Gets a copy of the current received buffer
|
|
*
|
|
* \param [IN]: buffer Buffer pointer
|
|
* \param [IN]: size Buffer size
|
|
*/
|
|
//void SX1276LoRaGetRxPacket( void *buffer, uint16_t *size );
|
|
|
|
/*!
|
|
* \brief Sets a copy of the buffer to be transmitted
|
|
*
|
|
* \param [IN]: buffer Buffer pointer
|
|
* \param [IN]: size Buffer size
|
|
*/
|
|
//void SX1276LoRaSetTxPacket( u8 * buffer, u16 size );
|
|
|
|
/*!
|
|
* \brief Gets the current RFState
|
|
*
|
|
* \retval rfState Current RF state [RF_IDLE, RF_BUSY,
|
|
* RF_RX_DONE, RF_RX_TIMEOUT,
|
|
* RF_TX_DONE, RF_TX_TIMEOUT]
|
|
*/
|
|
//uint8_t SX1276LoRaGetRFState( void );
|
|
|
|
/*!
|
|
* \brief Sets the new state of the RF state machine
|
|
*
|
|
* \param [IN]: state New RF state machine state
|
|
*/
|
|
//void SX1276LoRaSetRFState( u8 state );
|
|
|
|
/*!
|
|
* \brief Process the LoRa modem Rx and Tx state machines depending on the
|
|
* SX1276 operating mode.
|
|
*
|
|
* \retval rfState Current RF state [RF_IDLE, RF_BUSY,
|
|
* RF_RX_DONE, RF_RX_TIMEOUT,
|
|
* RF_TX_DONE, RF_TX_TIMEOUT]
|
|
*/
|
|
|
|
|
|
/* BEGIN: Added by Barry, 2014/3/4 */
|
|
|
|
/*
|
|
void write_LoRa_state(tRFLRStates cuState);
|
|
tRFLRStates read_LoRa_state(void);
|
|
void readTest(void);
|
|
uint32_t SX1276LoRaProcess( void );
|
|
void printRxEndInfo(void);
|
|
void printRxStartInfo(void);
|
|
void printTxEndInfo(void);
|
|
void printTxStartInfo(void);
|
|
void printRxData(void);
|
|
void printData(u8 *pBufer,u8 length);
|
|
*/
|
|
|
|
void config_GDOx_Map(st_GDOx_Config GDOx_Map);
|
|
void sx1276RxFinishProcess(void);
|
|
int8_t getPacketSnr(void);
|
|
double get_RxPacketRssi(int8_t RxPacketSnr);
|
|
|
|
u32 SX1276LoRaGetSymbolTs(uint8_t BwFlag ,uint8_t SF);
|
|
double SX1276LoRaGetTimeOnAir(u8 paylod);
|
|
uint32_t SX1276LoRaGetPayloadSymbNb(u8 paylod);
|
|
uint32_t SX1276LoRaGetTxTimeOut(void);
|
|
|
|
void SX1276LoRaSetPacketRxGain( uint8_t inputValue);
|
|
void SX1276LoRaSetPacketSnr( int8_t inputValue);
|
|
void SX1276LoRaSetPacketRssi( double inputValue);
|
|
u8 SX1276LoRaInitHopPeriod(void);
|
|
void SX1276LoRaStartTransmit(void);
|
|
void SX1276LoRa_Receive_Packet(u8 channel, bool wakeUp);
|
|
void SX1276LoRa_Send_Packet(u8 channel, bool wakeUp,u8 *PBuffer,u8 length);
|
|
void RxEndProcess(bool dataValid);
|
|
uint8_t SX1276LoRaGetRFState( void );
|
|
void SX1276StartSleep(void);
|
|
void set_half_period(u32 val);
|
|
u32 get_half_period(void);
|
|
void receiveRxData(u8 *buf, u8 *length);
|
|
void set_hop_Channel(u8 channel);
|
|
void SX1276LoRa_CAD_Scan(u8 channel);
|
|
void Lora_lowPower_Init(u32 period);
|
|
|
|
/* END: Added by Barry, 2014/3/4 */
|
|
#endif //__SX1276_LORA_H__
|
|
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|
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|
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